Figure 6.46 Example Of Idle Cycle Operation (Read After Write) - Renesas H8S/2368 Series Hardware Manual

Address bus
(area A)
(area B)
,
Data bus
(a) No idle cycle insertion

Figure 6.46 Example of Idle Cycle Operation (Read after Write)

Relationship between Chip Select (CS
system's load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.47. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A Bus cycle B
T T T T T
1 2 3 1 2
y
Long output floating time
(ICIS2 = 0)
CS) Signal and Read (RD CS CS
Bus cycle A
T
1
Address bus
(area A)
(area B)
Data bus
Data collision
(b) Idle cycle insertion
(ICIS2 = 1, initial value)
RD) Signal: Depending on the RD RD
Rev. 2.00, 05/03, page 181 of 820
Bus cycle B
T T T T T
2 3 i 1 2
Idle cycle