Renesas H8S/2368 Series Hardware Manual page 459

16-bit single-chip microcomputer
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Bit
Bit Name
Initial value
3
TGFD
0
2
TGFC
0
R/W
Description
1
R/(W)*
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD
input capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
When TCNT = TGRD while TGRD is functioning
as output compare register
When TCNT value is transferred to TGRD by
input capture signal while TGRD is functioning as
input capture register
[Clearing conditions]
When DTC is activated by TGID interrupt while
DISEL bit of MRB in DTC is 0
When 0 is written to TGFD after reading TGFD =
1
1
R/(W)*
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC
input capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
When TCNT = TGRC while TGRC is functioning
as output compare register
When TCNT value is transferred to TGRC by
input capture signal while TGRC is functioning as
input capture register
[Clearing conditions]
When DTC is activated by TGIC interrupt while
DISEL bit of MRB in DTC is 0
When 0 is written to TGFC after reading TGFC =
1
Rev. 2.00, 05/03, page 407 of 820

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