Operation; Pulse Output - Renesas H8S/2368 Series Hardware Manual

Bit Bit Name
4 —
3 OS3
2 OS2
1 OS1
0 OS0
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
12.4

Operation

12.4.1

Pulse Output

Figure 12.2 shows an example that the 8-bit timer is used to generate a pulse output with a
selected duty cycle. The control bits are set as follows:
[1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is
cleared at a TCORA compare match.
[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
Initial Value R/W
1 R
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
This bit is always read as 1 and cannot be
modified.
Output Select 3 and 2
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
Output Select 1 and 0
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Rev. 2.00, 05/03, page 481 of 820