Figure 7.5 Operation In Idle Mode; Table 7.6 Register Functions In Idle Mode - Renesas H8S/2368 Series Hardware Manual

by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
Table 7.6 Register Functions in Idle Mode
Register
23
MAR
23 15
H'FF IOAR
15
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.
Figure 7.5 illustrates operation in idle mode.
MAR
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer
ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The
maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.6 shows an example of the setting procedure for idle mode.
Function
DTDIR = 0 DTDIR = 1 Initial Setting
0
Source Destination
address address
register register
0
Destination Source
address address
register register
0
Transfer counter

Figure 7.5 Operation in Idle Mode

Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Rev. 2.00, 05/03, page 233 of 820
Operation
Fixed
Fixed
transfer; transfer
ends when count
reaches H'0000
IOAR