Burst Rom Interface; Basic Timing - Renesas H8S/2368 Series Hardware Manual

6.7

Burst ROM Interface

In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst
ROM interfacing performed. The burst ROM space enables ROM with burst access capability to
be accessed at high speed.
Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in
BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the
setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for
burst access.
Settings can be made independently for area 0 and area 1.
In burst ROM space, burst access covers only CPU read accesses.
6.7.1

Basic Timing

The number of access states in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and
CSACRH. When area 0 or area 1 is designated as burst ROM space, the settings in RDNCR and
CSACRL are ignored.
From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to
BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up
to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and
BSTS10 in BROMCR.
The basic access timing for burst ROM space is shown in figures 6.42 and 6.43.
Rev. 2.00, 05/03, page 176 of 820