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Section 9 I/O Ports
Table 9.1 summarizes the port functions. The pins of each port also have other functions such as
input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes
a data direction register (DDR) that controls input/output, a data register (DR) that stores output
data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR
or DDR register.
Ports A to E have a built-in pull-up MOS function and a pull-up MOS control register (PCR) to
control the on/off state of MOS input pull-up.
Ports 3 and A include an open-drain control register (ODR) that controls the on/off state of the
output buffer PMOS.
Ports 1 to 3, 5 (P50 to P53), and 8 (P81, P83, P85)can drive a single TTL load and 30 pF
capacitive load. Ports A to G can drive a single TTL load and 50 pF capacitive load.
All of the I/O ports can drive a Darlington transistor when outputting data.
Ports 1 and 2 are Schmitt-triggered inputs. Ports 4, 5, and A (PA4, PA5, PA6, PA7) are Schmitt-
triggered inputs when used as IRQ inputs.
Rev. 2.00, 05/03, page 299 of 820
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