Renesas H8S/2368 Series Hardware Manual page 48

Table 6.9 Pin States in Bus Released State ............................................................................ 192
Section 7 DMA Controller (DMAC)
Table 7.1 Pin Configuration................................................................................................... 201
Table 7.2 Short Address Mode and Full Address Mode (Channel 0) .................................... 202
Table 7.3 DMAC Activation Sources .................................................................................... 226
Table 7.4 DMAC Transfer Modes ......................................................................................... 228
Table 7.5 Register Functions in Sequential Mode ................................................................. 230
Table 7.6 Register Functions in Idle Mode............................................................................ 233
Table 7.7 Register Functions in Repeat Mode ....................................................................... 235
Table 7.8 Register Functions in Single Address Mode.......................................................... 238
Table 7.9 Register Functions in Normal Mode...................................................................... 241
Table 7.10 Register Functions in Block Transfer Mode .......................................................... 244
Table 7.11 DMAC Channel Priority Order.............................................................................. 264
Table 7.12 Interrupt Sources and Priority Order...................................................................... 268
Section 8 Data Transfer Controller (DTC)
Table 8.1 Relationship between Activation Sources and DTCER Clearing .......................... 281
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................ 283
Table 8.3 Chain Transfer Conditions..................................................................................... 286
Table 8.4 Register Function in Normal Mode ....................................................................... 286
Table 8.5 Register Function in Repeat Mode ........................................................................ 287
Table 8.6 Register Function in Block Transfer Mode............................................................ 288
Table 8.7 DTC Execution Status ........................................................................................... 292
Table 8.8 Number of States Required for Each Execution Status.......................................... 292
Section 9 I/O Ports
Table 9.1 Port Functions........................................................................................................ 300
Table 9.2 MOS Input Pull-Up States (Port A) ....................................................................... 347
Table 9.3 MOS Input Pull-Up States (Port B) ....................................................................... 351
Table 9.4 MOS Input Pull-Up States (Port C) ....................................................................... 355
Table 9.5 MOS Input Pull-Up States (Port D) ....................................................................... 358
Table 9.6 MOS Input Pull-Up States (Port E) ....................................................................... 362
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.1 TPU Functions ....................................................................................................... 374
Table 10.2 Pin Configuration................................................................................................... 377
Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3) .................................................................. 381
Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) ......................................................... 381
Table 10.5 TPSC2 to TPSC0 (Channel 0) ............................................................................... 382
Table 10.6 TPSC2 to TPSC0 (Channel 1) ............................................................................... 382
Table 10.7 TPSC2 to TPSC0 (Channel 2) ............................................................................... 383
Table 10.8 TPSC2 to TPSC0 (Channel 3) ............................................................................... 383
Table 10.9 TPSC2 to TPSC0 (Channel 4) ............................................................................... 384
Table 10.10 TPSC2 to TPSC0 (Channel 5) ............................................................................... 384
Table 10.11 MD3 to MD0 ......................................................................................................... 386
Table 10.12 TIORH_0 ............................................................................................................... 388
Rev. 2.00, 05/03, page xlviii of lii