Table of Contents
Advertisement
D.
Bus State during Execution of Instructions
Table D.1 shows the execution state of each instruction in this LSI.
[Explanation of Table Contents]
Instruction
1
R:W 2nd
[Legend]
R:B
Reading in bytes
R:W
Reading in words
W:B
Writing in bytes
W:W
Writing in words
:M
Bus right cannot be handed over immediately after this cycle
2nd
Address of second word (3rd and 4th bytes)
3rd
Address of third word (5th and 6th bytes)
4th
Address of fourth word (7th and 8th bytes)
5th
Address of fifth word (9th and 10th bytes)
NEXT
Start address of instruction immediately following the instruction being executed
EA
Effective address
VEC
Vector address
Figure D.1 shows the timing of the address bus, RD, HWR, and LWR during execution of the
sample instruction above (example in "Explanation of Table Contents") with an 8-bit bus, 3-state
access, and no wait.
2
3
1 state of inter-
R:W EA
nal operation
Order of execution
4
5
6
End of instruction
Read the effective address in words.
Read/write is not performed.
Read the second word of the instruction that is being executed in words.
Rev. 2.00, 05/03, page 795 of 820
7
8
Advertisement
Table of Contents
