Figure 7.28 Example Of Single Address Mode Transfer (Byte Write) - Renesas H8S/2368 Series Hardware Manual

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (write) is performed from an external device to
external 8-bit, 2-state access space.
Address bus
release

Figure 7.28 Example of Single Address Mode Transfer (Byte Write)

Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
DMA write DMA write
Bus Bus
release
DMA write DMA write
Bus Bus
release release
Rev. 2.00, 05/03, page 259 of 820
DMA
dead
Last transfer Bus
cycle release