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6.2
Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1
Pin Configuration
Name
Address strobe
Read
High write
Low write
Chip select 0
Chip select 1
Chip select 2/row address
strobe 2*
Chip select 3/row address
strobe 3*
Chip select 4
Chip select 5
Chip select 6
Chip select 7
Upper column address strobe* UCAS*
Lower column address strobe* LCAS*
Symbol
I/O
AS
Output
RD
Output
HWR
Output
LWR
Output
CS0
Output
CS1
Output
CS2/
Output
RAS2*
CS3/
Output
RAS3*
CS4
Output
CS5
Output
CS6
Output
CS7
Output
Output
Output
Function
Strobe signal indicating that normal space
is accessed and address output on address
bus is enabled.
Strobe signal indicating that normal space
is being read.
Strobe signal indicating that normal space
is written to, and upper half (D15 to D8) of
data bus is enabled or DRAM space write
enable signal.
Strobe signal indicating that normal space
is written to, and lower half (D7 to D0) of
data bus is enabled.
Strobe signal indicating that area 0 is
selected.
Strobe signal indicating that area 1 is
selected
Strobe signal indicating that area 2 is
selected, DRAM row address strobe signal
when area 2 is DRAM space or areas 2 to 5
are set as continuous DRAM space.
Strobe signal indicating that area 3 is
selected, DRAM row address strobe signal
when area 3 is DRAM space.
Strobe signal indicating that area 4 is
selected.
Strobe signal indicating that area 5 is
selected.
Strobe signal indicating that area 6 is
selected.
Strobe signal indicating that area 7 is
selected.
16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal.
16-bit DRAM space lower column address
strobe signal.
Rev. 2.00, 05/03, page 109 of 820
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