Renesas H8S/2368 Series Hardware Manual page 421

Bit Bit Name Initial Value
7 — 0
6 PG6DDR 0
5 PG5DDR 0
4 PG4DDR 0
3 PG3DDR 0
2 PG2DDR 0
1 PG1DDR 0
0 PG0DDR 1/0*
Note: * PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7.
R/W Description
— Reserved
•
W
Modes 1, 2, 4, and 7 (when EXPE = 1)
Pins PG6 and PG5 function as bus control
W
input/output pins (BREQ and BACK) when the
W
appropriate bus controller settings are made.
W
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR. Pin PG4
W
functions as the bus control input/output pin
W
(BREQO) when the appropriate bus controller
settings are made. Otherwise, when the CS7E bit is
W
set to 1, pin PG4 functions as the CS7 output pin
when PG4DDR is set to 1, and as an input port when
the bit is cleared to 0. When the CS7E bit is cleared
to 0, pin PG4 is an I/O port, and its function can be
switched with PG4DDR. When the CS output enable
bits (CS3E to CS0E) are set to 1, pins PG3 to PG0
function as CS output pins when the corresponding
PGDDR bit is set to 1, and as input ports when the bit
is cleared to 0. When CS3E to CS0E are cleared to
0, pins PG3 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
•
Mode 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Rev. 2.00, 05/03, page 369 of 820