Figure 6.4 Ras Signal Assertion Timing - Renesas H8S/2368 Series Hardware Manual

Address
RAST = 0
RAST = 1
,
(2-State Column Address Output Cycle, Full Access)
T
p
Row address
Figure 6.4 RAS RAS Signal Assertion Timing
RAS RAS
Bus cycle
T T
r c1
Column address
Rev. 2.00, 05/03, page 127 of 820
T
c2