Block Transfer Mode; Receive Data Sampling Timing And Reception Margin - Renesas H8S/2368 Series Hardware Manual

In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1
to invert the parity bit for both transmission and reception.
14.7.3

Block Transfer Mode

Operation in block transfer mode is the same as that in normal Smart Card interface, except for the
following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
after transmission start.
• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but
since error signal transfer is not performed, this flag is always cleared to 0.
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
14.7.4

Receive Data Sampling Timing and Reception Margin

Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive
clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, or 256 times the bit rate (fixed at 16 times in normal
asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the
falling edge of the start bit using the basic clock, and performs internal synchronization. As
shown in figure 14.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or
128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is
given by the following formula.
1
M = | (0.5 – ) – (L – 0.5) F –
2N
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
| D – 0.5 |
(1 + F) |
N
100%
Rev. 2.00, 05/03, page 569 of 820