Input/Output Pin; Figure 13.1 Block Diagram Of Wdt; Table 13.1 Pin Configuration - Renesas H8S/2368 Series Hardware Manual

(interrupt request
Internal reset signal*
Legend
TCSR
TCNT
RSTCSR
Note: * An internal reset signal can be generated by the register setting.
13.2

Input/Output Pin

Table 13.1 describes the WDT output pin.

Table 13.1 Pin Configuration

Name
Watchdog timer overflow
Rev. 2.00, 05/03, page 496 of 820
Interrupt
WOVI
control
signal)
Reset
control
RSTCSR
: Timer control/status register
: Timer counter
: Reset control/status register

Figure 13.1 Block Diagram of WDT

Symbol
WDTOVF
Overflow
Clock
Clock
select
TCNT TSCR
Module bus
WDT
I/O Function
Output Outputs counter overflow signal in watchdog
timer mode
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
sources
Bus
interface