• P25/PO5*
1
/TIOCB4/TMO1
The pin function is switched as shown below according to the combination of the TPU channel
4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1
and CCLR0 in TCR_4), bit NDER5*
TCSRI of TMR.
TPU channel 4
(1) in table below
settings
OS3 to OS0
P25DDR
1
NDER5*
Pin function
TIOCB4 output
Notes: *1 Not supported by the H8S/2366.
*2 TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
TPU channel 4
settings
MD3 to MD0
IOB3 to IOB0
B'0000
B'0100
B'1xxx
CCLR1, CCLR0
Output function
x: Don't care
1
in NDERL, bit P25DDR, and bits OS3 to USO in
—
All 0
—
—
P25 input
(2)
(1)
B'0000 to B'01xx
B'0001 to
B'0011
B'0101 to
B'0111
—
—
—
Output
compare
output
(2) in table below
0
1
—
0
P25 output
TIOCB4 input*
(2)
(2)
B'0010
—
B'xx00
—
—
—
—
All 1
One value is 1
1
1
1
PO5 output*
TMO1 output
2
(1)
B'0011
Other than B'xx00
Other than
B'10
PWM mode
2 output
Rev. 2.00, 05/03, page 317 of 820
—
—
(2)
B'10
—