C Bus Control Register B (Iccrb); Table 15.2 Transfer Rate - Renesas H8S/2368 Series Hardware Manual

Table 15.2 Transfer Rate

Bit3 Bit2 Bit1 Bit0
CKS3 CKS2 CKS1 CKS0
0 0 0 0
1
1 0
1
1 0 0
1
1 0
1
1 0 0 0
1
1 0
1
1 0 0
1
1 0
1
2
15.3.2 I

C Bus Control Register B (ICCRB)

ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in I
Bit Bit Name Initial Value R/W
7 BBSY 0
Rev. 2.00, 05/03, page 594 of 820
Clock Transfer Rate
φ φ φ φ =8MHz
φ/28
286kHz
φ/40
200kHz
φ/48
167kHz
φ/64
125kHz
φ/168
47.6kHz
φ/100
80.0kHz
φ/112
71.4kHz
φ/128
62.5kHz
φ/56
143kHz
φ/80
100kHz
φ/96
83.3kHz
φ/128
62.5kHz
φ/336
23.8kHz
φ/200
40.0kHz
φ/224
35.7kHz
φ/256
31.3kHz
Description
R/W Bus Busy
This bit enables to confirm whether the I
or released and to issue start and stop conditions in master
mode. This bit is set to 1 when the SDA level changes from
high to low under the condition of SCL = high, assuming
that the start condition has been issued. This bit is cleared
to 0 when the SDA level changes from low to high under
the condition of SCL = high, assuming that the stop
condition has been issued. Write 1 to BBSY and 0 to SCP
to issue a start condition. Follow this procedure when also
re-transmitting a start condition. Write 0 to BBSY and 0 to
SCP to issue a stop condition. To issue a start/stop
condition, use the MOV instruction.
φ φ φ φ =10MHz φ φ φ φ =20MHz
357kHz 714kHz
250kHz 500kHz
208kHz 417kHz
156kHz 313kHz
59.5kHz 119kHz
100kHz 200kHz
89.3kHz 179kHz
78.1kHz 156kHz
179kHz 357kHz
125kHz 250kHz
104kHz 208kHz
78.1kHz 156kHz
29.8kHz 59.5kHz
50.0kHz 100kHz
44.6kHz 89.3kHz
39.1kHz 78.1kHz
2
C control.
φ φ φ φ =25MHz φ φ φ φ =33MHz
893kHz 1179kHz
625kHz 825kHz
521kHz 688kHz
391kHz 516kHz
149kHz 196kHz
250kHz 330kHz
223kHz 295kHz
195kHz 258kHz
446kHz 589kHz
313kHz 413kHz
260kHz 344kHz
195kHz 258kHz
74.4kHz 98.2kHz
125kHz 165kHz
112kHz 147kHz
97.7kHz 129kHz
2
C bus is occupied