Register
Name
Reset
PEPCR
Initialized
P3ODR
Initialized
PAODR
Initialized
SMR_3
Initialized
BRR_3
Initialized
SCR_3
Initialized
TDR_3
Initialized
SSR_3
Initialized
RDR_3
Initialized
SCMR_3
Initialized
SMR_4
Initialized
BRR_4
Initialized
SCR_4
Initialized
TDR_4
Initialized
SSR_4
Initialized
RDR_4
Initialized
SCMR_4
Initialized
TCR_3
Initialized
TMDR_3
Initialized
TIORH_3
Initialized
TIORL_3
Initialized
TIER_3
Initialized
TSR_3
Initialized
TCNT_3
Initialized
TGRA_3
Initialized
TGRB_3
Initialized
TGRC_3
Initialized
TGRD_3
Initialized
TCR_4
Initialized
TMDR_4
Initialized
TIOR_4
Initialized
TIER_4
Initialized
TSR_4
Initialized
High-
Clock
Speed
Division Sleep
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Module
All Module
Software
Stop
Clock Stop
Standby
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Rev. 2.00, 05/03, page 725 of 820
Hardware
Standby
Module
Initialized
PORT
Initialized
Initialized
Initialized
SCI_3
Initialized
Initialized
Initialized
Initialized
SCI_4
Initialized
Initialized
Initialized
Initialized
TPU_3
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
TPU_4
Initialized
Initialized
Initialized
Initialized