Figure 24.16 Dram Access Timing: Three-State Access (Rast = 1) - Renesas H8S/2368 Series Hardware Manual

A23 to A0
,
,
Read
D15 to D0
,
Write
D15 to D0
,
Notes:
timing: when DDS = 0
timing: when RAST = 1

Figure 24.16 DRAM Access Timing: Three-State Access (RAST = 1)

T T
p r
t
AD
t t
AS2 AH2
t
CSD2
t
PCH1
T T
c1 c2
t
AD
t
AS3
t
OED2
t
AA5
t
AC7
t
t WCS2
WRD2
t
WDD
t
WDS2
t
DACD1
Rev. 2.00, 05/03, page 755 of 820
T
c3
t
CSD3
t
AH3
t
CASD1
t
CASD2
t
CASW2
t
t
OED1
AC2
t
t
RDS2
RDH2
t
WCH2
t
WRD2
t
WDH3
t
DACD2