Renesas H8S/2368 Series Hardware Manual page 14

Item
19.1 Features
• Size
• Flash memory emulation
by RAM*
19.3 Block Configuration
Figure 19.5 384-kbyte
Flash Memory Block
Configuration (Modes 3, 4,
and 7)
19.5.5 RAM Emulation
Register (RAMER)
19.7 Flash Memory
Emulation in RAM
19.8.2 Erase/Erase-Verify
21.1.1 System Clock
Control Register (SCKCR)
21.2.1 Connecting a
Crystal Oscillator
Rev. 2.00, 05/03, page xiv of lii
Page Revision (See Manual for Details)
645 Table amended.
Product Classification
H8S/2368 Series
Note * added
Note: * This function is not supported by the
651 Note deleted.
656 Note added.
Note:
662 Note added.
Note:
663 Note 4 added.
Note: 4. This function is not supported by the
666 Description amended in the 8th line.
4. The watchdog timer (WDT) is set to prevent
overerasing due to program runaway, etc.
677 Bits 2, 1, and 0 discription amended.
Bit Bit Name
2 SCK2
1 SCK1
0 SCK0
678 Description added in the 6th line.
An AT-cut parallel-resonance type should be used.
When a clock is supplied with a crystal resonator
connected, the frequency of the crystal resonator
should be 8 MHz to 25 MHz.
ROM Size ROM Address
HD64F2367 384 kbytes H'000000 to H'05FFFF (Modes 3, 4, and 7)
HD64F2366
H8S/2367 or H8S/2366.
This function is not supported by the
H8S/2367 or H8S/2366.
This function is not supported by the
H8S/2367 or H8S/2366.
H8S/2367 or H8S/2366.
Initial Value R/W Description
0 R/W System Clock Select 2 to 0
0 R/W
Select the division ratio.
0 R/W
000: 1/1
001: 1/2
010: 1/4
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
11X: Setting prohibited