Renesas H8S/2368 Series Hardware Manual page 40

Figure 7.11 Operation in Normal Mode.................................................................................... 242
Figure 7.12 Example of Normal Mode Setting Procedure ........................................................ 243
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) ............................................... 245
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ............................................... 246
Figure 7.15 Operation Flow in Block Transfer Mode............................................................... 247
Figure 7.16 Example of Block Transfer Mode Setting Procedure ............................................ 248
Figure 7.17 Example of DMA Transfer Bus Timing ................................................................ 249
Figure 7.18 Example of Short Address Mode Transfer ............................................................ 250
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) ......................................... 251
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ........................................ 252
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)......................... 253
Example of DREQ Pin Falling Edge Activated Normal Mode Transfer ............... 254
Figure 7.22
Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer ... 255
Figure 7.23
Example of DREQ Pin Low Level Activated Normal Mode Transfer .................. 256
Figure 7.24
Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer ...... 257
Figure 7.25
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)....................................... 258
Figure 7.27 Example of Single Address Mode (Word Read) Transfer ..................................... 258
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)...................................... 259
Figure 7.29 Example of Single Address Mode Transfer (Word Write) .................................... 260
Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer ... 261
Figure 7.30
Example of DREQ Pin Low Level Activated Single Address Mode Transfer ...... 262
Figure 7.31
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function ................ 263
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function.............. 264
Figure 7.34 Example of Multi-Channel Transfer ...................................................................... 265
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt.................................................................................................... 266
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation ..................... 267
Figure 7.37 Example of Procedure for Clearing Full Address Mode........................................ 268
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt..................................... 269
Figure 7.39 DMAC Register Update Timing ............................................................................ 270
Figure 7.40 Contention between DMAC Register Update and CPU Read ............................... 270
Example in which Low Level is Not Output at TEND Pin.................................... 272
Figure 7.41
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC.......................................................................................... 276
Figure 8.2 Block Diagram of DTC Activation Source Control............................................... 281
Figure 8.3 Correspondence between DTC Vector Address and Register Information............ 282
Figure 8.4 Correspondence between DTC Vector Address and Register Information............ 282
Figure 8.5 Flowchart of DTC Operation ................................................................................. 285
Figure 8.6 Memory Mapping in Normal Mode....................................................................... 287
Figure 8.7 Memory Mapping in Repeat Mode........................................................................ 288
Figure 8.8 Memory Mapping in Block Transfer Mode........................................................... 289
Figure 8.9 Operation of Chain Transfer .................................................................................. 290
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode).................. 291
Rev. 2.00, 05/03, page xl of lii