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7.11.2
Port A Data Register (PADR)
PADR stores output data for the port A pins.
Bit
Bit Name
7
PA7DR
6
PA6DR
5
PA5DR
4
PA4DR
3
PA3DR
2
PA2DR
1
PA1DR
0
PA0DR
7.11.3
Port A Register (PORTA)
PORTA reflects the pin state in port A and cannot be modified.
Bit
Bit Name
7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
0
PA0
Note:
* Determined by the states of the PA7 to PA0 pins.
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Description
PADR stores output data for the port A pins that
are used as the general output ports.
Description
When this register is read, the bit that is set in
PADDR is read as the value of PADR. The bit
that is cleared in PADDR is read as the pin
state.
Rev. 1.00, 09/03, page 199 of 704
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