Peripheral Clock Select Register (Pcsr); Bus Master Interface; Table 9.2 Clock Selection Of Pwmx - Renesas H8S/2437 Hardware Manual

9.3.4

Peripheral Clock Select Register (PCSR)

PCSR and the CKS bit in DACR select the operating speed.
Bit Bit Name Initial Value
7 PWCKXC 0
6 PWCKXB 0
5 PWCKXA 0

4 to 0
2
1 PWCKB 0
0 PWCKA 0
Table 9.2 Clock Selection of PWMX
PWCKXC PWCKXB
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
9.4

Bus Master Interface

DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and
read from as follows.
(1) Write
When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written to, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written to the register.
R/W Description
R/W PWMX Clock Select
R/W
Select a clock cycle with the CKS bit in DACR of the
R/W
PWMX being 1. See table 9.2.
R/W Reserved
The initial value should not be changed.
R/W PWM Clock Select
R/W
PWCKXA Resolution (T)
0 Operates on the system clock cycle (t
1 Operates on the system clock cycle (t
0 Operates on the system clock cycle (t
1 Operates on the system clock cycle (t
0 Operates on the system clock cycle (t
1 Operates on the system clock cycle (t
0 Operates on the system clock cycle (t
1 Setting prohibited
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Rev. 1.00, 09/03, page 231 of 704
) x 2
) x 64
) x 128
) x 256
) x 1024
) x 4096
) x 16384