Figure 13.4 Timing Chart For Pwm Decoding; Table 13.5 Examples Of Tcr Settings; Table 13.6 Examples Of Tcorb (Pulse Width Threshold) Settings - Renesas H8S/2437 Hardware Manual

Table 13.5 Examples of TCR Settings

Bit Abbreviation
7 CMIEB
6 CMIEA
5 OVIE
4, 3 CCLR1, CCLR0
2 to 0 CKS2 to CKS0

Table 13.6 Examples of TCORB (Pulse Width Threshold) Settings

φ φ φ φ : 10 MHz
H'07 0.8 µs
H'0F 1.6 µs
H'1F 3.2 µs
H'3F 6.4 µs
H'7F 12.8 µs
IHI signal
PDC signal
TCNT
TCORB
(threshold)
Counter reset
caused by
IHI signal
Contents
0
0
0
11
001
φ φ φ φ : 12 MHz
0.67 µs
1.33 µs
2.67 µs
5.33 µs
10.67 µs
IHI signal is tested
at compare-match
Counter clear
caused by
TCNT overflow

Figure 13.4 Timing Chart for PWM Decoding

Description
Interrupts due to a compare-match and overflow are
disabled
TCNT is cleared by the rising edge of the external
reset signal (IHI signal)
Internal clock: Incremented on φ
φ φ φ φ : 16 MHz
0.5 µs
1 µs
2 µs
4 µs
8 µs
At the 2nd compare-match,
IHI signal is not tested
Rev. 1.00, 09/03, page 381 of 704
φ φ φ φ : 20 MHz
0.4 µs
0.8 µs
1.6 µs
3.2 µs
6.4 µs