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• Single-Chip Mode (EXPE = 0)
TIOCA2S
TPU channel
2 setting
P26DDR
Pin function
P26 input pin
TPU channel
2 setting
MD3 to MD0
IOA3 to IOA0
B'0000
B'0100
B'1xxx
CCLR1,
CCLR0
Output
function
[Legend]
x: Don't care
Notes: 1. When TIOCA2S = 0, MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1, this pin functions
as the TIOCA2 input pin.
2. Output is disabled for TIOCB2.
• P25/TIOCB1/TCLKC/A13/AD13
When the TIOCB1/TCLKCS bit in PTCNT2 is cleared to 0, this pin can be used as the
TIOCB1/TCLKC pin.
According to operating modes, the TPU channel 1 settings by the MD3 to MD0 bits in
TMDR_1, the IOB3 to IOB0 bits in TIOR_1, and the CCLR1 and CCLR0 bits in TCR_1, and
the combination of the TPSC2 to TPSC0 bits in TCR_0 and TCR_2, the TIOCB1/TCLKCS
bit, and the P25DDR bit, pin functions change as follows.
0
Table below (2)
0
1
P26 output pin
1
TIOCA2 input pin*
(2)
(1)
B'0000, B'01xx
B'0001 to B'0011
B'0101 to B'0111
Output compare
output
Table below (1)
TIOCA2 output
P26 input pin
pin
(2)
(1)
B'001x
B'0010
B'xx00
Other than
B'xx00
PWM*
mode 1
output
Rev. 1.00, 09/03, page 147 of 704
1
0
1
P26 output pin
(1)
(2)
B'0011
Other than B'xx00
Other than
B'01
B'01
2
PWM
mode 2
output
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