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The difference between the erasing procedures in user program mode and user boot mode depends
on whether the MAT is switched or not as shown in figure 20.15.
MAT switching is enabled by writing a specific value to FMATS. However, note that while the
MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until
MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is
read is undetermined. Perform MAT switching in accordance with the description in section 20.6,
Switching between User MAT and User Boot MAT.
Except for MAT switching, the erasing procedure is the same as that in user program mode.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Storable Area for Procedure Program and
Program Data.
20.4.4
Storable Area for Procedure Program and Program Data
In the descriptions in the previous section, storable areas for the programming/erasing procedure
programs and program data are assumed to be in the on-chip RAM. However, storable areas can
be placed in other areas, such as part of flash memory which is not to be programmed or erased, or
somewhere in the external address space by using the following conditions.
(1) Conditions that Apply to Programming/Erasing
1. The on-chip programming/erasing program is downloaded from the address in the on-chip
RAM specified by FTDAR, therefore, this area is not available for use.
2. The on-chip programming/erasing program will use 128 bytes at the maximum as a stack. So,
make sure that this area is secured.
3. Download by setting the SCO bit to 1 will lead to switching of the MAT. If, therefore, this
operation is used, it should be executed from the on-chip RAM.
4. The flash memory is accessible until the start of programming or erasing, that is, until the
result of downloading has been determined. When in a mode in which the external address
space is not accessible, such as single-chip mode, the required procedure programs, NMI
handling vector, and NMI handler should be transferred to the on-chip RAM before
programming/erasing of the flash memory starts.
5. The flash memory is not accessible during programming/erasing operations, therefore, the
operation program downloaded to the on-chip RAM is executed. The NMI-handling vector and
processing programs such as that which activate the operation program, and NMI handler
should thus be stored in on-chip RAM other than flash memory or the external bus space.
6. After programming/erasing, an access to the flash memory is prohibited until FKEY is cleared.
The reset period (RES = 0) must be in place for more than 100 µs when the LSI mode is
changed to reset on completion of a programming/erasing operation.
Rev. 1.00, 09/03, page 568 of 704
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