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3.3
Operating Mode Descriptions
3.3.1
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The initial mode after a reset is single-chip mode, to use the external address space, set the EXPE
bit in MDCR to 1.
Normal Extended Mode:
After a reset, ports 1 and 2 become input ports.
The address bus can be output when the corresponding port data direction register (DDR) is set to
1. Port 3 is a data bus, part of port 9 and port A become a bus control signal. When the ABWn bit
in BCRAn is cleared to 0, port 6 becomes the data bus. (n = 1 to 3)
Multiplex Extended Mode:
When using an 8-bit bus, regardless of the data direction register (DDR) setting of port 2, it
becomes an address output and data input/output port. Port 1 can be used as a general port.
When using a 16-bit bus, regardless of the data direction register (DDR) setting of port 1 or 2, they
become address output and data input/output ports.
Rev. 1.00, 09/03, page 54 of 704
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