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Clock input
φ/1
Internal clock:
φ/4
φ/16
φ/64
φ/256
φ/1024
TCLKA
External clock:
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0:
TIOCA0
TIOCB0
TIOCC0
TIOCD0
Channel 1:
TIOCA1
TIOCB1
TIOCA2
Channel 2:
TIOCB2
[Legend]
TSTR:
Timer start register
TSYR:
Timer synchro register
TCR:
Timer control register
TMDR:
Timer mode register
Rev. 1.00, 09/03, page 300 of 704
TIOR (H, L):
Timer I/O control registers (H, L)
TIER:
Timer interrupt enable register
TSR:
Timer status register
TGR (A, B, C, D):
Timer general registers (A, B, C, D)
Figure 12.1 Block Diagram of TPU
Internal data bus
A/D conversion
start request signal
Interrupt request signals
Channel 0:
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1:
TGI1A
TGI1B
TCI1V
TCI1U
Channel 2:
TGI2A
TGI2B
TCI2V
TCI2U
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