Table of Contents
Advertisement
• PA4/FTIC_0/CLAMPO
According to the combination of the CLOE bit in TCONRO of the timer connection_0 and the
PA4DDR bit, the pin function is switched as shown below.
When the ICICE bit in TIER of the FRT_0 is set to 1, this pin functions as the FTIC_0 input
pin.
CLOE
PA4DDR
Pin function
• PA3/FTOB_0/CBLANK
According to the combination of the CBOE bit in TCONRO of the timer connection_0, the
OEB bit in TOCR of the FRT_0, and the PA3DDR bit, the pin function is switched as shown
below.
CBOE
OEB
PA3DDR
Pin function
PA3 input pin
• PA2/TMO0_0/ExTIOCC0/ExTCLKA
When the TIOCC0/TCLKAS bit in PTCNT2 is set to 1, this pin can be used as the
ExTIOCC0/ExTCLKA pin.
According to the TPU channel 0 settings by the OS3 to OS0 bits in TCSR of the TMR0_0, the
MD3 to MD0 bits in TMDR_0, the IOC3 to IOC0 bits in TIORL_0, and the CCLR2 to CCLR0
bits in TCR_0, and the combination of the TPSC2 to TPSC0 bits in TCR_0 to TCR_2, the
TIOCC0/TCLKAS bit, and the PA2DDR bit, the pin function is switched as shown below.
TIOCC0/
TCLKAS
TPU channel
0 setting
OS3 to OS0
PA2DDR
0
Pin function
PA2 input
pin
Rev. 1.00, 09/03, page 202 of 704
0
PA4 input pin
0
0
0
1
PA3 output pin
0
All 0
At least one
bit is set to 1
1
PA2 output
TMO0_0
pin
output pin
0
1
PA4 output pin
FTIC_0 input pin
1
FTOB_0 output pin
Table (2)
0
PA2 input pin PA2 output pin
ExTIOCC0 input pin*
ExTCLKA input pin*
1
CLAMPO output pin
1
CBLANK output pin
1
Table (1)
1
ExTIOCC0
output pin
1
2
Advertisement
Table of Contents
