Buffered Input Capture Input Timing; Figure 10.9 Buffered Input Capture Timing - Renesas H8S/2437 Hardware Manual

10.5.5

Buffered Input Capture Input Timing

ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 10.9 shows how
input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and
IEDGC are set to different values (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1),
so that input capture is performed on both the rising and falling edges of FTIA.
φ
FTIA
Input capture
signal
FRC
ICRA
ICRC
Even when ICRC or ICRD is used as a buffer register, its input capture flag is set according to the
selected edge of its input capture signal. For example, if ICRC is used as the ICRA buffer register,
when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, the
ICFC flag will be set, and if the ICICE bit is set at this time, an interrupt will be requested. The
FRC value will not be transferred to ICRC, however. In buffered input capture, if either set of two
registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read
when the input capture input signal occurs, input capture is delayed by one system clock (φ).
Figure 10.10 shows the timing when BUFEA = 1.
n
M n
m M

Figure 10.9 Buffered Input Capture Timing

n + 1
Rev. 1.00, 09/03, page 255 of 704
N N + 1
n N
M n