Timer Control Register (Tcr) - Renesas H8S/2437 Hardware Manual

Common Registers:
• Timer start register (TSTR)
• Timer synchro register (TSYR)
12.3.1

Timer Control Register (TCR)

TCR controls the TCNT operation for each channel. The TPU has a total of three TCR registers,
one for each channel (channels 0 to 2). TCR settings should be made only when TCNT operation
is stopped.
Bit Bit Name Initial Value
7 CCLR2 0
6 CCLR1 0
5 CCLR0 0
4 CKEG1 0
3 CKEG0 0
2 TPSC2 0
1 TPSC1 0
0 TPSC0 0
R/W Description
R/W Counter Clear 2 to 0
R/W Select the TCNT counter clearing source. See tables 12.3
and 12.4 for details.
R/W
R/W Clock Edge 1, 0
R/W Select the input clock edge. When the internal clock is
counted using both edges, the input clock cycle is 1/2
(example: φ/4 both edges = φ/2 rising edge). If phase
counting mode is used on channels 1 and 2, this setting
is ignored and the phase counting mode setting has
priority. Internal clock edge selection is valid when the
input clock is φ/4 or slower. This setting is ignored if the
input clock is φ/1 and the rising edge counting is selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
[Legend] x: Don't care
R/W Timer Prescaler 2 to 0
R/W Select the TCNT counter clock. The clock source can be
selected independently for each channel. See tables 12.5
R/W
to 12.7 for details.
Rev. 1.00, 09/03, page 305 of 704