Compare-Match Count Mode; Input Capture Operation; Figure 11.11 Timing Of Input Capture Operation - Renesas H8S/2437 Hardware Manual

11.7.2

Compare-Match Count Mode

When bits CKS2 to CKS0 in TCRX are B'100, TCNTX counts the occurrence of compare-match
A for the TMRY. TMRY and TMRX are controlled independently. Conditions such as setting of
the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in
accordance with the settings for the TMRY and TMRX.
11.7.3

Input Capture Operation

The TMRX has input capture registers (TICR, TICRR, and TICRF). A narrow pulse width can be
measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMRX
input capture input signal) is detected after its rising edge has been detected, the value of TCNTX
at that time is transferred to both TICRR and TICRF.
Input Timing of Input Capture Signal:
Figure 11.11 shows the timing of the input capture operation.
φ
TMRIX
Input capture
signal
TCNTX
TICRR
TICRF
If the input capture signal is input while TICRR and TICRF are being read, the input capture
signal is delayed by one system clock (φ) cycle. Figure 11.12 shows the timing of this operation.
n
M
m

Figure 11.11 Timing of Input Capture Operation

n + 1
n
Rev. 1.00, 09/03, page 289 of 704
N
n
m
N
N + 1