C Bus Control Register B (Iccrb); Table 17.2 Transfer Rate - Renesas H8S/2437 Hardware Manual

Table 17.2 Transfer Rate

Bit 3 Bit 2 Bit 1
CKS3 CKS2 CKS1 CKS0 Clock
0 0 0
1
1 0
1
1 0 0
1
1 0
1
2
17.3.2 I

C Bus Control Register B (ICCRB)

ICCRB issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
a reset in IIC control.
Bit Bit Name Initial Value R/W
7 BBSY 0
Rev. 1.00, 09/03, page 480 of 704
Bit 0
φ φ φ φ = 8 MHz
φ/28
0 286 kHz
φ/40
1 200 kHz
φ/48
0 167 kHz
φ/64
1 125 kHz
φ/168
0 47.6 kHz
φ/100
1 80.0 kHz
φ/112
0 71.4 kHz
φ/128
1 62.5 kHz
φ/56
0 143 kHz
φ/80
1 100 kHz
φ/96
0 83.3 kHz
φ/128
1 62.5 kHz
φ/336
0 23.8 kHz
φ/200
1 40.0 kHz
φ/224
0 35.7 kHz
φ/256
1 31.3 kHz
Description
R/W Bus Busy
There are two functions: a flag function which indicates
whether the I
which issues start and stop conditions in master mode.
This bit is set to 1 when the SDA level changes from high
to low under the condition of SCL = high, assuming that the
start condition has been issued. This bit is cleared to 0
when the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop condition
has been issued. Write 1 to BBSY and 0 to SCP to issue a
start condition. Also follow this procedure when re-
transmitting a start condition. Write 0 to BBSY and 0 to
SCP to issue a stop condition. To issue a start/stop
condition, use the MOV instruction.
Transfer Rate
φ φ φ φ = 10 MHz
357 kHz
250 kHz
208 kHz
156 kHz
59.5 kHz
100 kHz
89.3 kHz
78.1 kHz
179 kHz
125 kHz
104 kHz
78.1 kHz
29.8 kHz
50.0 kHz
44.6 kHz
39.1 kHz
2
C bus is occupied or released and a function
φ φ φ φ = 20 MHz
714 kHz
500 kHz
417 kHz
313 kHz
119 kHz
200 kHz
179 kHz
156 kHz
357 kHz
250 kHz
208 kHz
156 kHz
59.5 kHz
100 kHz
89.3 kHz
78.1 kHz