Switching Between User Mat And User Boot Mat; Figure 20.16 Transitions To Error Protection State - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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Figure 20.16 shows state transitions to and from the error-protection state.
Program mode
Erase mode
Read disabled,
programming/erasing
enabled, FLER = 0
Error occurred
Error protection mode
programming/erasing disabled,
20.6

Switching between User MAT and User Boot MAT

It is possible to switch between the user MAT and user boot MAT. However, the following
procedure is required because these MATs are allocated to address 0.
(Switching to the user boot MAT disables programming and erasing. Programming of the user
boot MAT should take place in boot mode or programmer mode.)
1. MAT switching by FMATS should always be executed in the on-chip RAM.
2. To ensure that the MAT that has been switched to is accessible, execute four NOP instructions
in the on-chip RAM immediately after writing to FMATS in the on-chip RAM (this prevents
access to the flash memory during MAT switching).
3. If an interrupt has occurred during switching, there is no guarantee of which memory MAT is
being accessed. Always mask the maskable interrupts before switching between MATs. In
addition, configure the system so that NMI interrupts do not occur during MAT switching.
4. After the MATs have been switched, take care because the interrupt vector table will also have
been switched. If interrupt processing is to be the same before and after MAT switching,
transfer the interrupt-processing routines to the on-chip RAM and set the WEINTE bit in
FCCS to place the interrupt-vector table in the on-chip RAM.
5. Memory sizes of the user MAT and user boot MAT are different. When accessing the user
boot MAT, do not access addresses above the top of its 8-kbyte memory space. If an access is
made beyond the 8-kbyte space, the undefined value will be read.
Rev. 1.00, 09/03, page 580 of 704
= 0 or
Software standby mode
Read enabled,
software standby mode
FLER = 1

Figure 20.16 Transitions to Error Protection State

Reset or hardware
= 0
(Hardware protection)
programming/erasing disabled,
= 0 or
= 0
Error protection mode
(Software standby)
Read disabled,
Cancel
programming/erasing disabled,
FLER = 1
Program/erase interface
register is in its initial state.
standby
Read disabled,
FLER = 0
Program/erase interface
register is in its initial state.

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