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TPU channel 1 setting
MD3 to MD0
IOA3 to IOA0
CCLR1, CCLR0
Output function
[Legend]
x: Don't care
Notes: 1. When TIOCA1S = 1, MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx, this
pin functions as the TIOCA1 input pin.
2. Output is disabled for TIOCB1.
• PA6/FTCI_0/HFBACKI
According to the setting of the PA6DDR bit, the pin function is switched as shown below.
When the CKS1 and CKS0 bits in TCR of the FRT_0 are all set to 1, this pin functions as the
FTCI_0 input pin. When the SIMOD1 and SIMOD0 bits (IHI signal) in TCONRI of the timer
connection_0 are cleared to B'00, this pin functions as the HFBACKI input pin.
PA6DDR
Pin function
• PA5/FTIB_0/VFBACKI
According to the setting of the PA5DDR bit, the pin function is switched as shown below.
When the ICIBE bit in TIER of the FRT_0 is set to 1, this pin functions as the FTIB_0 input
pin. When the SIMOD1 and SIMOD0 bits (IVI signal) in TCONRI of the timer connection_0
are cleared to B'00, this pin functions as the VFBACKI input pin.
PA5DDR
Pin function
(2)
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
B'1xxx
Output compare
output
0
PA6 input pin
0
PA5 input pin
(2)
(1)
B'001x
B'0010
B'xx00
Other than
B'xx00
PWM
mode 1
2
output*
PA6 output pin
FTCI_0 input pin
HFBACKI input pin
PA5 output pin
FTIB_0 input pin
VFBACKI input pin
Rev. 1.00, 09/03, page 201 of 704
(1)
(2)
B'0011
Other than B'xx00
Other than
B'01
B'01
PWM mode
2 output
1
1
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