Figure 6.20 Bus Timing For 16-Bit, 2-State Data Access Space (5) (Word Access, With Address Wait) - Renesas H8S/2437 Hardware Manual

Read Cycle Write Cycle
Address Data Address
Data
T T T T T T T T T T
1 AW 2 3 4 1 AW 2 3 4
AD15 to AD8
Data
Address Address
Data
AD7 to AD0
Data
Address Address
Data
Note: n = 1 to 3
Figure 6.20 Bus Timing for 16-Bit, 2-State Data Access Space (5)
(Word Access, with Address Wait)
Rev. 1.00, 09/03, page 120 of 704