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TPU channel 0
setting
MD3 to MD0
IOB3 to IOB0
CCLR2 to CCLR0
Output function
[Legend]
x: Don't care
Notes: 1. When TIOCD0/TCLKBS = 1, MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx, this
pin functions as the TIOCD0 input pin.
2. When TIOCD0/TCLKBS = 1 and TPSC2 to TPSC0 in one of TCR_0 to TCR2 = B'101,
this pin functions as the TCLKB input pin. When TIOCB1/TCLKCS = 1 and phase-count
mode is set to the TCR channel 1, this pin functions as the TCLKB input pin.
• P96/φ
According to the setting of the P96DDR bit, the pin function is switched as shown below.
P96DDR
Pin function
• P95/AS/AH
According to the operating mode and combination of the ASOE bit and the P95DDR bit, the
pin function is switched as shown below.
• Extended Mode (EXPE = 1)
ASOE
P95DDR
Pin function
• Single-Chip Mode (EXPE = 0)
P95DDR
Pin function
(2)
(1)
B'0000
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
B'1xxx
Output compare
output
Normal Extended Mode (ADMXE = 0)
0
0
P95 input pin
P95 output pin
P95 input pin
(2)
B'0010
0
P96 input pin
1
AS output pin
0
(2)
(1)
B'0011
B'xx00
Other than B'xx00
Other than
B'110
PWM mode
2 output
1
φ output pin
Multiplex Extended
Mode (ADMXE = 1)
1
AH output pin
1
P95 output pin
Rev. 1.00, 09/03, page 193 of 704
(2)
B'110
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