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• Single-Chip Mode (EXPE = 0)
TIOCB2/
TCLKDS
TPU channel
2 setting
P27DDR
Pin function
P27 input pin
TPU channel
(2)
2 setting
MD3 to MD0
IOB3 to IOB0
B'0000
B'0100
B'1xxx
CCLR1,
CCLR0
Output
function
[Legend]
x: Don't care
Notes: 1. When TIOCB2/TCLKDS = 0, MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1, this pin
functions as the TIOCB2 input pin.
2. When TIOCB2/TCLKDS = 0 and TPSC2 to TPSC0 in TCR_0 = B'111, this pin functions
as the TCLKD input pin. When TIOCB2/TCLKDS = 0 and phase-count mode is set to
the TCR channel 2, this pin functions as the TCLKD input pin.
• P26/TIOCA2/A14/AD14
When the TIOCA2S bit in PTCNT2 is cleared to 0, this pin can be used as the TIOCA2 pin.
According to operating modes, the TPU channel 2 settings by the MD3 to MD0 bits in
TMDR_2, the IOA3 to IOA0 bits in TIOR_2, and the CCLR1 and CCLR0 bits in TCR_2, and
the combination of the TIOCA2S bit and the P26DDR bit, pin functions change as follows.
• Extended Mode (EXPE = 1)
Normal Extended Mode (ADMXE = 0)
P26DDR
Pin function
P26 input pin
Rev. 1.00, 09/03, page 146 of 704
0
Table below (2)
0
1
P27 output pin
1
TIOCB2 input pin*
TCLKD input pin*
(1)
B'0000, B'01xx
B'0001 to B'0011
B'0101 to B'0111
Output compare
output
0
A14 output pin
Table below (1)
TIOCB2 output
pin
2
(2)
(2)
B'0010
B'xx00
Multiplex Extended Mode (ADMXE = 1)
1
1
TIOCA2 input pin*
1
0
P27 input pin
P27 output pin
(1)
B'0011
Other than B'xx00
Other than
B'10
PWM mode
2 output
AD14 I/O pin
1
(2)
B'10
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