Renesas H8S/2437 Hardware Manual page 26

Section 12 16-Bit Timer Pulse Unit (TPU)
Figure 12.1 Block Diagram of TPU............................................................................................ 300
Figure 12.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ...................... 325
Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)].................. 325
Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)].............. 326
Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] ....... 326
Figure 12.6 Example of Counter Operation Setting Procedure .................................................. 327
Figure 12.7 Free-Running Counter Operation ............................................................................ 328
Figure 12.8 Periodic Counter Operation..................................................................................... 329
Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match.............. 329
Figure 12.10 Example of 0 Output/1 Output Operation ............................................................. 330
Figure 12.11 Example of Toggle Output Operation ................................................................... 330
Figure 12.12 Example of Setting Procedure for Input Capture Operation.................................. 331
Figure 12.13 Example of Input Capture Operation..................................................................... 331
Figure 12.14 Example of Synchronous Operation Setting Procedure ........................................ 332
Figure 12.15 Example of Synchronous Operation...................................................................... 333
Figure 12.16 Compare Match Buffer Operation ......................................................................... 334
Figure 12.17 Input Capture Buffer Operation............................................................................. 334
Figure 12.18 Example of Buffer Operation Setting Procedure................................................... 335
Figure 12.19 Example of Buffer Operation (1)........................................................................... 335
Figure 12.20 Example of Buffer Operation (2)........................................................................... 336
Figure 12.21 Cascaded Operation Setting Procedure ................................................................. 337
Figure 12.22 Example of Cascaded Operation (1)...................................................................... 338
Figure 12.23 Example of Cascaded Operation (2)...................................................................... 338
Figure 12.24 Example of PWM Mode Setting Procedure .......................................................... 340
Figure 12.25 Example of PWM Mode Operation (1) ................................................................. 340
Figure 12.26 Example of PWM Mode Operation (2) ................................................................. 341
Figure 12.27 Example of PWM Mode Operation (3) ................................................................. 342
Figure 12.28 Example of Setting Procedure for Phase Counting Mode ..................................... 343
Figure 12.29 Example of Phase Counting Mode 1 Operation .................................................... 344
Figure 12.30 Example of Phase Counting Mode 2 Operation .................................................... 345
Figure 12.31 Example of Phase Counting Mode 3 Operation .................................................... 346
Figure 12.32 Example of Phase Counting Mode 4 Operation .................................................... 347
Figure 12.33 Count Timing in Internal Clock Operation............................................................ 350
Figure 12.34 Count Timing in External Clock Operation........................................................... 350
Figure 12.35 Output Compare Output Timing............................................................................ 351
Figure 12.36 Input Capture Input Signal Timing........................................................................ 351
Figure 12.37 Counter Clear Timing (Compare Match) .............................................................. 352
Figure 12.38 Counter Clear Timing (Input Capture) .................................................................. 352
Figure 12.39 Buffer Operation Timing (Compare Match).......................................................... 353
Figure 12.40 Buffer Operation Timing (Input Capture) ............................................................. 353
Figure 12.41 TGI Interrupt Timing (Compare Match) ............................................................... 354
Rev. 1.00, 09/03, page xxvi of xxxviii