Figure 6.17 Bus Timing For 16-Bit, 2-State Data Access Space (2) (Even Byte Access, Without Address Wait) - Renesas H8S/2437 Hardware Manual

Read Cycle Write Cycle
Address Data Address
Data
T T T T T T T T
1 2 3 4 1 2 3 4
AD15 to AD8
Address Address
Data
Data
AD7 to AD0
Address
Address
Note: n = 1 to 3
Figure 6.17 Bus Timing for 16-Bit, 2-State Data Access Space (2)
(Even Byte Access, without Address Wait)
Rev. 1.00, 09/03, page 117 of 704