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18.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
18.4.1
Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or
external trigger input.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion
stops and the A/D converter enters the wait state.
18.4.2
Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels:
maximum four channels or maximum eight channels. Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by software, TPU, or external trigger input, A/D
conversion starts on the first channel in the specified channel set.
The consecutive A/D conversion on maximum four channels (SCANE = 1 and SCANS = 0) or
on maximum eight channels (SCANE = 1 and SCANS = 1) can be selected. When the
consecutive A/D conversion is performed on the four channels, the A/D conversion starts on
AN0 when CH3 = 0 and CH2 = 0, AN4 when CH3 = 0 and CH2 = 1, AN8 when CH3 = 1 and
CH2 = 0, or AN12 when CH3 = 1 and CH2 = 1. When the consecutive A/D conversion is
performed on the eight channels, the A/D conversion starts on AN0 when CH3 = 0 and CH2 =
0 and on AN8 when CH3 = 1 and CH2 = 0.
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the corresponding A/D data register to each channel.
3. When conversion for all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. Conversion for
the first channel in the channel set starts again.
Rev. 1.00, 09/03, page 514 of 704
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