Figure 6.1 Block Diagram Of Bus Controller - Renesas H8S/2437 Hardware Manual

Multiplex Extension:
The address output pins and data input/output pins are multiplex pins
• Minimization of number of pins
It is possible to minimize the number of pins necessary for expansion by multiplexing the
address output pins and data input/output pins.
• Usable areas
Areas 1, 2, and 3 are all usable
• Multiplex extended bus interface
In the address cycle there are 2-state access fixed areas
In the data cycle 2-state access areas or 3-state access areas are able to be selected
The address cycle or data cycle can be independently inserted into the program wait state
• Idle cycle insert
Idle cycle insert is possible during the external write cycle, directly after external read cycle
External bus control signals
[Legend]
BCR: Bus control register
BCRA1: Basic area/area 1 control register
BCRA2: Area 2 control register
BCRA3: Area 3 control register
Rev. 1.00, 09/03, page 92 of 704

Figure 6.1 Block Diagram of Bus Controller

Bus
controller
BCR BCRA1
BCRA2 BCRA3
Wait
controller
Internal control signals
Bus mode signal