Renesas H8S/2437 Hardware Manual page 17

Section 14 Duty Measurement Circuit.............................................................. 399
14.1 Features .............................................................................................................................399
14.2 Input/Output Pins ..............................................................................................................401
14.3 Register Descriptions ........................................................................................................402
14.3.1 Free-Running Counter (TWCNT)........................................................................402
14.3.2 Input Capture Register (TWICR).........................................................................402
14.3.3 Duty Measurement Control Register 1 (TWCR1) ...............................................403
14.3.4 Duty Measurement Control Register 2 (TWCR2) ...............................................404
14.4 Operation...........................................................................................................................406
14.4.1 Duty Measurement for External Event Signal .....................................................406
14.5 Operation Timing..............................................................................................................407
14.5.1 TWCNT Count Timing........................................................................................407
14.5.2 TWCNT Clear Timing by Setting START Bit ....................................................407
14.5.3 Count Start Timing for Duty Measurement .........................................................408
14.5.4 Capture Timing during Duty Measurement .........................................................408
14.5.5 Clear Timing for START Bit when Duty Measurement Ends .............................409
14.5.6 Set Timing for Duty Measurement End Flag (ENDF) .........................................409
14.5.7 Set Timing for Overflow Flag (OVF) ..................................................................410
14.6 Interrupt Sources ...............................................................................................................410
14.7 Usage Notes ......................................................................................................................411
14.7.1 Conflict between TWCNT Write and Increment .................................................411
14.7.2 Write to START Bit during Free-Running Counter Operation............................411
14.7.3 Switching of Internal Clock and TWCNT Operation ..........................................412
14.7.4 Switching of External Event Signal and Operation of Edge Detection Circuit....414
Section 15 Watchdog Timer (WDT)................................................................. 417
15.1 Features .............................................................................................................................417
15.2 Register Descriptions ........................................................................................................418
15.2.1 Timer Counter (TCNT)........................................................................................418
15.2.2 Timer Control/Status Register (TCSR) ................................................................418
15.3 Operation...........................................................................................................................420
15.3.1 Watchdog Timer Mode ........................................................................................420
15.3.2 Interval Timer Mode ............................................................................................421
15.3.3 Internal Reset Signal Generation Timing.............................................................422
15.4 Interrupt Sources ...............................................................................................................422
15.5 Usage Notes ......................................................................................................................423
15.5.1 Notes on Register Access.....................................................................................423
15.5.2 Conflict between Timer Counter (TCNT) Write and Increment..........................424
15.5.3 Changing Values of CKS2 to CKS0 Bits.............................................................424
15.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................424
Rev.1.00, 09/03, page xvii of xxxviii