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TPU channel
(2)
0 setting
MD3 to MD0
IOA3 to
B'0000
IOA0
B'0100
B'1xxx
CCLR2 to
CCLR0
Output
function
[Legend]
x: Don't care
Notes: 1. When TIOCC0/TCLKAS = 1, MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx, this
pin functions as the TIOCC0 input pin.
2. When TIOCC0/TCLKAS = 1 and TPSC2 to TPSC0 in one of TCR_0 to TCR_2 = B'100,
this pin functions as the TCLKA input pin. When TIOCC0/TCLKAS = 1 and phase-count
mode is set to the TCR channel 1, this pin functions as the TCLKA input pin.
3. Output is disabled for TIOCD0. When BFA = 1 or BFB = 1 in TMDR0, output is disabled
and the setting is the same as (2).
• PA1/TMOY_0/ExPW7/SCK4
When the PW7S bit in PTCNT0 is set to 1, this pin can be used as the ExPW7 pin.
According to the combination of the C/A bit in SMR of the SCI_4, the CKE0 and CKE1 bits in
SCR, the OS3 to OS0 bits in TCSR of the TMRY_0, the OE7 bit in PWOER of the PWM, the
PW7S bit, and the PA1DDR bit, the pin function is switched as shown below.
CKE1
C/A
CKE0
OS3 to OS0
PA1DDR
0
PW7S
OE7
Pin function
PA1
input pin
(1)
B'0000
B'0001 to B'0011
B'0101 to B'0111
Output compare
output
0
0
All 0
1
0
1
0
PA1
PA1
output
output
pin
pin
(2)
(1)
B'001x
B'0010
B'xx00
Other than
B'xx00
PWM mode
2
1 output*
0
At least
one bit is
set to 1
1
PW7
TMOY_0
output
output
pin
pin
Rev. 1.00, 09/03, page 203 of 704
(1)
B'0011
Other than B'xx00
Other than
B'101
B'101
PWM mode 2
output
1
1
SCK4
SCK4
SCK4
output
output
input pin
pin
pin
(2)
1
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