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16.6.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 16.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the receive data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR
is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF
flag remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. If the RXI interrupt processing routine reads the receive data transferred to RDR
before reception of the next receive data has finished, continuous reception can be enabled.
Synchronization
clock
Serial data
RDRF
ORER
RXI interrupt
request
generated
Figure 16.18 Example of SCI Receive Operation in Clocked Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF flags to 0 before resuming reception. Figure 16.19 shows a sample
flowchart for serial data reception.
Bit 7
Bit 0
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
1 frame
Bit 7
Bit 0
Bit 1
RXI interrupt
request generated
Rev. 1.00, 09/03, page 463 of 704
Bit 6
Bit 7
ERI interrupt request
generated by overrun
error
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