Instruction Set; Table 2.1 Instruction Classification - Renesas H8S/2437 Hardware Manual

2.6

Instruction Set

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1 Instruction Classification
Function Instructions
Data transfer MOV
POP*
LDM, STM
MOVFPE*
Arithmetic ADD, SUB, CMP, NEG
operations
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
TAS*
MAC, LDMAC, STMAC, CLRMAC
Logic operations AND, OR, XOR, NOT
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
Branch Bcc*
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
Block data transfer EEPMOV
Notes: B: byte size; W: word size; L: longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP respectively. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn
and MOV.L ERn, @-SP respectively.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
1 1
, PUSH*
3 3
, MOVTPE*
4
2
, JMP, BSR, JSR, RTS
Size
B/W/L
W/L
L
B
B/W/L
B
B/W/L
L
B/W
W/L
B
—
B/W/L
B
—
—
Total:
Rev. 1.00, 09/03, page 31 of 704
Types
5
23
4
8
14
5
9
1
69