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16-Bit, 3-State Data Access Space:
Figures 6.22 to 6.24 show bus timings for a 16-bit, 3-state access space. When a 16-bit access
space is accessed, the address bus uses all buses (AD15 to AD0), the upper half (AD15 to AD8) of
the data bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Data
cycle wait states can be inserted.
T
AD15 to AD8
AD7 to AD0
Note:
n = 1 to 3
Figure 6.22 Bus Timing for 16-Bit, 3-State Data Access Space (1)
Rev. 1.00, 09/03, page 122 of 704
Read Cycle
Data
Address
T
T
T
T
1
AW
2
3
Address
Address
(Even Byte Access, with Address Wait)
Address
T
T
T
T
4
DSW
5
1
Data
Address
Address
Write Cycle
Data
T
T
T
T
AW
2
3
4
Data
T
DSW
5
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