Table of Contents
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2.7.8
Memory Indirect-@@aa:8 ................................................................................ 45
2.7.9
Effective Address Calculation ............................................................................. 46
2.8
Processing States............................................................................................................... 49
2.9
Usage Note........................................................................................................................ 50
2.9.1
Usage Notes on Bit-Wise Operation Instructions ................................................ 50
Section 3 MCU Operating Modes .....................................................................51
3.1
Operating Mode Selection ................................................................................................ 51
3.2
Register Descriptions ........................................................................................................ 52
3.2.1
Mode Control Register (MDCR) ......................................................................... 52
3.2.2
System Control Register (SYSCR) ...................................................................... 53
3.3
Operating Mode Descriptions ........................................................................................... 54
3.3.1
Mode 7 ................................................................................................................. 54
3.3.2
Pin Functions ....................................................................................................... 55
3.4
Memory Map .................................................................................................................... 56
Section 4 Exception Handling ...........................................................................57
4.1
Exception Handling Types and Priority ............................................................................ 57
4.2
Exception Sources and Exception Vector Table ............................................................... 58
4.3
Reset ................................................................................................................................. 59
4.3.1
Reset exception handling ..................................................................................... 59
4.3.2
Interrupts after Reset............................................................................................ 60
4.3.3
On-Chip Peripheral Functions after Reset Release .............................................. 60
4.4
Traces................................................................................................................................ 61
4.5
Interrupts........................................................................................................................... 61
4.6
Trap Instruction................................................................................................................. 62
4.7
Stack Status after Exception Handling.............................................................................. 63
4.8
Usage Note........................................................................................................................ 64
Section 5 Interrupt Controller............................................................................65
5.1
Features............................................................................................................................. 65
5.2
Input/Output Pins .............................................................................................................. 67
5.3
Register Descriptions ........................................................................................................ 67
5.3.1
Interrupt Control Register (INTCR) .................................................................... 68
5.3.2
Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 69
5.3.3
IRQ Enable Register (IER) .................................................................................. 71
5.3.4
IRQ Sense Control Registers (ISCR)................................................................... 72
5.3.5
IRQ Status Register (ISR).................................................................................... 74
5.3.6
Software Standby Release IRQ Enable Register (SSIER) ................................... 75
5.4
Interrupt Sources............................................................................................................... 75
5.4.1
External Interrupt Sources ................................................................................... 75
5.4.2
Internal Interrupts ................................................................................................ 76
5.5
Interrupt Exception Handling Vector Table...................................................................... 76
Rev.1.00, 09/03, page x of xxxviii
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