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System CKS2
CKS1
TMRY
0
1
1
0
TMRX
0
0
0
0
0
1
0
1
1
0
Common 1
0
1
1
1
1
Note:
* If the TMR0 clock input is set as the TCNT1 overflow signal and the TMR1 clock input is
set as the TCNT0 compare-match signal simultaneously, a count-up clock cannot be
generated. Similarly, If the TMRY clock input is set as the TCNTX overflow signal and
the TMRX clock input is set as the TCNTY compare-match signal simultaneously, a
count-up clock cannot be generated. Simultaneous setting of these two conditions
should therefore be avoided.
Rev. 1.00, 09/03, page 276 of 704
TCR
CKS0
ICKS1
1
0
0
1
0
1
0
1
0
1
TECR
Description
ICKS0
Increments at falling edge of internal
clock φ/2048
Increments at overflow signal from
TCNTX*
Disables clock input
Increments at falling edge of internal
clock φ
Increments at falling edge of internal
clock φ/2
Increments at falling edge of internal
clock φ/4
Increments at compare-match A from
TCNTY*
Increments at rising edge of external
clock
Increments at falling edge of external
clock
Increments at both rising and falling
edges of external clock
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