Timer Status Register (Tsr) - Renesas H8S/2437 Hardware Manual

Bit Bit Name Initial Value
1 TGIEB 0
0 TGIEA 0
12.3.5

Timer Status Register (TSR)

TSR indicates the status of each channel. The TPU has a total of three TSR registers, one for each
channel.
Bit Bit Name Initial Value R/W
7 TCFD 1

6 1
5 TCFU 0
Rev. 1.00, 09/03, page 320 of 704
R/W Description
R/W TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB disabled
1: Interrupt requests (TGIB) by TGFB enabled
R/W TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA disabled
1: Interrupt requests (TGIA) by TGFA enabled
Description
R Count Direction Flag
Status flag that indicates the direction in which TCNT
counts in channels 1 and 2. In channel 0, bit 7 is
reserved. It is always read as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
R Reserved
This bit is always read as 1 and cannot be modified.
R/(W)* Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. In channel 0, bit 5 is reserved. It is
always read as 0 and cannot be modified.
[Setting condition]
When the TCNT value underflows (change from H'0000
to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1