Figure 6.21 Bus Timing For 16-Bit, 2-State Data Access Space (6) (Word Access, Without Address Wait) - Renesas H8S/2437 Hardware Manual

AD15 to AD8
AD7 to AD0
Note: n = 1 to 3
Figure 6.21 Bus Timing for 16-Bit, 2-State Data Access Space (6)
(Word Access, without Address Wait)
Read Cycle
Address Data
T T T T
1 2 3 4
Address
Data
Address
Data
Write Cycle
Address
Data
T T T T
1 2 3 4
Address
Data
Address
Data
Rev. 1.00, 09/03, page 121 of 704